The invention relates to logical binary circuitry and circuitry having particular utility as a decode circuit for use in solid-state matrix memory arrays such as a PROM, ROM or RAM.
Solid-state matrix memory arrays in which information is stored are well known in the art. The matrix array, as a single integrated circuit comprises rows and columns of parallel electrical conductors formed with memory cells (or memory elements) connecting the intersections or cross-over points of the rows and columns. The RAM will have a memory cell at each cross-over point, whereas the ROM will have a memory element at, at least certain cross-over points. The complementary address decode circuitry, in accordance with the invention finds particular utility when employed in the circuitry utilized to address a matrix memory array.
It will be readily appreciated by persons skilled in the art, by virtue of the detailed description setforth hereinafter, that the circuitry of the invention may be employed in applications other than matrix memories. It will further be apparent, from the detailed description hereinafter, that a portion or all of the complementary address decode circuit in accordance with the invention may be employed as a binary logic circuit for accepting a plurality of binary inputs and providing one or more logical binary outputs which are respectively logical binary functions of said inputs.